1. Field of the Invention
The present invention relates to memory devices, and more specifically, to memory devices having both volatile and non-volatile memory devices.
2. Background of the Invention
Manufacturers of memory components are often requested by their customers to provide non-volatile information within volatile memory components. The non-volatile information may include serial numbers, device type, lot number, date processed, customer specific information, etc. In some cases, there are a large number of non-volatile memory elements dedicated to storing the non-volatile information.
Non-volatile memory elements presently are not integrated with volatile memory elements or components. The term xe2x80x9cnon-volatile memory elementxe2x80x9d shall be defined herein for the purposes of this invention to mean a one-time programmable memory element. The term xe2x80x9cvolatile memory elementxe2x80x9d shall be defined herein for the purposes of this invention to mean a multi-time programmable memory element. The term xe2x80x9cintegratedxe2x80x9d shall be defined herein for the purposes of this invention to mean that the non-volatile memory elements are coupled to the same bit lines that the volatile memory elements are coupled (e.g., a cell of a volatile memory section shares a bit line or bit line pair with a cell of a non-volatile memory section). Because the non-volatile and volatile memory components of conventional memory systems are not integrated, access to each section of memory (i.e., non-volatile and volatile memory) is performed on separate electrical paths that are multiplexed. Because access to each memory section of memory is created by a multiplexing operation, the non-volatile and volatile memory is not considered to be integrated. Multiplexing allows for reading the stored information in either the non-volatile or the volatile memory elements from the same input/output port, but not the same reading device. In general, drivers are utilized to read from the non-volatile memory and a sense amplifier is utilized to read from the volatile memory. Additionally, these non-volatile memory elements can be relatively big and bulky and not interface easily with the volatile memory elements due to the different reading devices.
To overcome the problems of contemporary memory having non-integrated, non-volatile and volatile memory elements, the two types of memory components are integrated. The term xe2x80x9cintegratedxe2x80x9d shall be defined herein for the purposes of this invention to mean that the non-volatile memory elements are coupled to the same bit lines that the volatile memory elements are coupled. The integration of the two types of memory creates a small, compact solution with a minimum number of elements. The integration of the two memory types further allows for a simple interface that utilizes a single reading device (e.g., a sense amplifier).
One embodiment according to the principles of the present invention is a memory device having a first and a second memory section. The first and the second memory sections are coupled via bit lines. The first memory section may be static or dynamic random access memory. The second memory section includes current path elements capable of being substantially permanently opened. The second memory section may further include at least one fuse.
A second embodiment according to the principles of the present invention is an integrated circuit having at least one bit line pair shared by volatile and non-volatile memory elements and at least one word line coupled to each memory element. The memory elements are organized in a matrix configuration, the bit lines forming columns of memory cells and the word lines forming rows of memory cells. A first type and a second type of memory element share at least one bit line pair. The first type of memory element may be a static or dynamic random access memory and the second type of memory element is read only memory. The second type of memory may include at least one fuse.
Another embodiment according to the principles of the present invention includes a system having a processor and a memory. The memory includes a first memory type and a second memory type. The memory further includes a sense amplifier shared by both the first and second memory type. The first memory type is volatile memory and the second memory type is non-volatile memory. The second memory type may include at least one fuse.
The present invention further includes a method of pre-laser testing a non-volatile memory element integrated within a volatile memory. At least one logic voltage level is applied to the non-volatile memory element. The non-volatile memory element is selectively accessed and a logic level stored within the non-volatile memory elements is read. Prior to reading, bit lines are precharged.